Welcome and Introduction - Lorena Anghel, TIMA Laboratory, Program Chair Nanoarch 2017

Keynote

“DARPA Has Seen the Future of Computing … And It’s Analog …” Wired Magazine (PDF Abstract) - Dan Hammerstrom (Bio)

Break

Session 1: Spintronic & Neural Networks
Moderator: Lorena Anghel, TIMA Laboratory

A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance. Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Odilia Coi and Pascal Benoit.

SkyNet: Memristor-based 3D IC for Artificial Neural Networks. Sachin Bhat, Sourabh Kulkarni, Jiajun Shi, Mingyu Li and Csaba Andras Moritz.

Mixing Circuit based on Neural Associative Memories and Nanoelectronic 1S1R Cells. Arne Heittmann and Tobias G. Noll.

Spatio-temporal Learning with Arrays of Analog Nanosynapses. Christopher H Bennett, Damien Querlioz and Jacques Olivier-Klein.

Lunch

Session 2: Poster Pitch

Design and Operational Assessment of an Intra-Cell Hybrid L2 Cache. Fabrizio Lombardi, Weiqiang Liu, Jie Han and Linbin Chen.

L^3EP: Low Latency, Low Energy Program-and-Verify for Triple-Level Cell Phase Change Memory. Ali Alsuwaiyan and Kartik Mohanram.

Transient Model with Interchangeability for Dual-Gate Ambipolar CNTFET Logic Design. Xuan Hu and Joseph S. Friedman.

A Compact 8-bit Adder Design using In-Memory Memristive Computing: Towards Solving the Feynman Grand Challenge. Sumit Kumar Jha, Sunny Raj and Dwaipayan Chakraborty.

Automated Synthesis of Compact Multiplier Circuits for in-Memory Computing using ROBDDs. Amad Ul Hassen, Sumit Kumar Jha and Dwaipayan Chakraborty.

Linear Regression based Multi-State Logic Decomposition Approach for Efficient Hardware Implementation. Wafi Danesh and Mostafizur Rahman.

VerilogA Compact Model of a ME-MTJ Based XNOR/NOR Gate. Nishtha Sharma, Andrew Marshall and Jonathan Bird.

Memcapacitive Reservoir Computing. Dat Tran and Christof Teuscher.

A Logic-in-Memory Design with 3-Terminal Magnetic Tunnel Junction Function Evaluators for Convolutional Neural Networks. Sumit Dutta, Saima Siddiqui, Felix Büttner, Luqiao Liu, Caroline Ross and Marc Baldo.

High Performance and Energy-Efficient In-Memory Computing Architecture based on SOT-MRAM. Zhezhi He, Shaahin Angizi, Farhana Parveen and Deliang Fan.

Polymorphic Spintronic Logic Gates for Hardware Security Primitives – Device Design and Performance Benchmarking. Shaloo Rakheja and Nickvash Kani.

Break

Session 8: Memories
Session Moderator: Sorin Cotofana, Delft University of Technology

Architecture, Design and Technology Guidelines for Crosspoint Memories. Alexandre Levisse, Pablo Royer, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau and Jean-Michel Portal.

Ultra High Density 3D SRAM Cell Design in Stacked Horizontal Nanowire (SN3D) Fabric. Naveen Kumar Macha, Sandeep Geedipally and Mostafizur Rahman.

Break

Session 9: Devices and circuits II
Session Moderator: Csaba Andras Moritz, University of Massachussets Amherst

AOI-Based Data-Centric Circuits for Near-Memory Processing. Fabrizio Lombardi and Salin Junsangsri.

Power-Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS. Jiajun Shi, Mingyu Li and Csaba Andras Moritz.

Energy Efficient Computation using Injection Locked Bias-Field Free Spin-Hall Nano-Oscillator Array with Shared Heavy Metal. Karthik Yogendra, Minsuk Koo and Kaushik Roy.

A self-calibrating sense amplifier fora true random number generator using hybrid FinFET-Straintronic MTJ. Sudipta Bhuin, Joseph Sweeney, Samuel Pagliarini, Ayan Biswas and Lawrence Pileggi.

Closing - Csaba Andras Moritz, University of Massachussets Amherst