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Conference Venue:
Esplanade Room
Hotel Commonwealth
500 Commonwealth Avenue
Boston, MA 02215
Phone: (617) 532-5009

Important Deadlines:

Submission Deadline:
April 10, 2015
April 20, 2015

April 27, 2015

Acceptance Notification:
May 10, 2015
May 20, 2015

Final Version Due:
June 1, 2015

Early Registration:
June 1, 2015
June 5, 2015

July 8-10, 2015


  • Nanoarch 2016 will be held in Beijing, China. Click here for NANOARCH 2016.

  • NANOARCH 2015 Awards
  • Best Paper Award: Zhixi Yang, Jie Han and Fabrizio Lombardi, "Transmission Gate-based Approximate Adders for Inexact Computing".
  • Best Student Paper Award: Aaron Germuth and Alex Aravind, "From Kekule Cells to Molecular Switches".

NANOARCH 2015 is the leading conference on post-CMOS nanocircuits, nanoarchitectures, emerging nanoscale CMOS, and nanoscale fabrics in general. Both experimental and theoretical works are sought after.

Panoramic BostonNANOARCH is the annual cross-disciplinary forum for the discussion of novel post-CMOS nanocomputing directions and emerging nanoscale CMOS. The symposium seeks papers on innovative ideas for solutions to the principal challenge facing integrated electronics in the 21st century - how to design, fabricate, and integrate nanosystems to overcome the fundamental limitations of CMOS. In particular, such systems could (1) contain unconventional nanodevices with unique capabilities, including directions beyond simple switches, (2) introduce new logic and memory concepts, (3) involve novel circuit styles, (4) introduce new concepts for computing, (5) reconfigure and/or mask faults at much higher rates than in CMOS, (6) explore security architectures with nanotechnology, (7) involve new paradigms for manufacturing, and (8) rethink the methodologies and design tools involved.

This symposium includes several exciting sessions and opportunities for interaction. In addition to Regular papers presenting original techniques / directions, it invites the community to also submit Nanofabric Progress Updates giving a progress update of their nanofabrics directions to date across devices, circuits, architecture and manufacturability aspects - e.g. 2D/3D nanowire, magnonic, memristor, CNT, graphene, FinFETs, and QCA based directions.

In addition, Concept papers are invited from the broader nanotechnology community to highlight promising nanomaterial, nanodevice, nanomanufacturing, and integration ideas with application potential in nanoscale architectures.

Example topics (both theoretical and experimental) of interest include (but are not limited to):

  • Novel nanodevices and manufacturing/integration ideas with a focus on nanoarchitectures
  • Nanoelectronic circuits, nanofabrics, computing paradigms and nanoarchitectures
  • 2D/3D/hybrid nanodevice integration and manufacturing, with variability, defect and fault tolerance
  • Nanodevice and nanocircuit models, methodologies and computer aided design tools
  • Fundamental limits of computing at the nanoscale

Authors are invited to submit papers of 6 pages in length for the Regular, nano CMOS, Reliability, Nanofabrics Progress Updates, and 2 pages in length for Concept Sessions. We sincerely hope you can participate in NANOARCH 2015. Should you have any questions, please contact us using the links to the left

    Proceedings from the previous NANOARCH symposiums are available online at IEEE Xplore

    Final versions of accepted papers will be included in official NANOARCH 2015 symposium proceedings, and the conference content will be submitted for inclusion into IEEE Xplore as well as other Abstracting and Indexing (A&I) databases.

    Symposium Sponsors: