spacer
home
spacer
committee
spacer
call for papers
spacer
author info
spacer
submit papers
spacer
registrationspacer
Accommodations spacer
past conferences
spacer
contact us


Conference Venue:
Esplanade Room
Hotel Commonwealth
500 Commonwealth Avenue
Boston, MA 02215
Phone: (617) 532-5009


Important Deadlines:

Submission Deadline:
April 10, 2015
April 20, 2015

April 27, 2015

Acceptance Notification:
May 10, 2015
May 20, 2015

Final Version Due:
June 1, 2015

Early Registration:
June 1, 2015
June 5, 2015



Symposium:
July 8-10, 2015






 
 

NANOARCH 2015 PROGRAM


  Day One

8:15 - 8:45 AM

Breakfast

8:45 - 9:00 AM

Welcome / Opening Remarks

9:00 - 10:00 AM

Keynote

Future Information Processing: From Nanodevices to Nanosystems (PDF Abstract)- Victor Zhirnov and Ralph Cavin (Bio)(Presentation)

10:00 AM

Session I: 3D Memory

10:00 - 10:30 AM

Architecting Energy Efficient Crossbar-Based Memristive Random-Access Memories. Miguel Angel Lastras-Montaño, Amirali Ghofrani and Kwang-Ting Cheng

10:30 - 10:50 AM

An Architecture-level Cache Simulation Framework Supporting Advanced PMA STT-MRAM. Bi Wu, Yuanqing Cheng, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres and Weisheng Zhao

10:50 - 11:10 AM

MFNW: A Flip-N-Write Architecture for Multi-Level Cell Non-Volatile Memories. Ali Alsuwaiyan and Kartik Mohanram

11:10 - 11:30 AM Break
11:30 AM

Session II: Concept Paper Session A

11:30-11:45 AM

Lossy Frequency Selective Surfaces for Gas Sensing Using ZnO Films. Colin Pardue, Madhavan Swaminathan and John Balaguru

11:30-12:00 PM

Fundamental Limits of Energy Dissipation in Spintronic Interconnects Using Optical Spin Pumpin. Shaloo Rakheja

12:00-12:15 PM

Wave-Based Device Scaling Concept for Brain-Like Energy Efficiency and Integration. Yasunao Katayama, Toshiyuki Yamane, Daiju Nakano, Ryosho Nakane and Gouhei Tanaka

12:15-12:30 PM

Physically Equivalent Magneto-Electric Nanoarchitecture for Probabilistic Reasoning. Santosh Khasanvis, Mingyu Li, Mostafizur Rahman, Mohammad Salehi Fashami, Ayan K. Biswas, Jayasimha Atulasimha, Supriyo Bandyopadhyay and Csaba Andras Moritz

12:30 - 1:45 PM Lunch
1:45 PM Session III: Computing with Non-Volatile Memory
1:45 - 2:15 PM

Robust Magnetic Full-Adder with Voltage Sensing 2T/2MTJ Cell. Erya Deng, You Wang, Zhaohao Wang, Jacques-Olivier Klein, Bernard Dieny, Guillaume Prenat and Weisheng Zhao

2:15 - 2:45 PM Hierarchical Composition of Memristive Networks for Real-Time Computing. Jens Bürger, Alireza Goudarzi, Darko Stefanovic and Christof Teuscher
2:45 - 3:05 PM A Sudden Power-Outage Resilient Nonvolatile Microprocessor for Immediate System Recovery. Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi and Takahiro Hanyu
3:05 PM

Session IV: NEMS Design

3:05 - 3:25 PM

NEM Relay Design with Biconditional Binary Decision Diagrams. Winston Haaswijk, Luca Amaru, Pierre-Emmanuel Gaillardon and Giovanni De Micheli

3:25 - 3:55 PM

NEMsCAM: A Novel CAM Cell based on Nano-Electro-Mechanical Switch and CMOS for Energy Efficient TLBs. Azam Seyedi, Vasileios Karakostas, Stefan Cosemans, Adrian Cristal, Mario Nemirovsky and Osman Unsal

3:55 - 4:25 PM

Poster Pitch (10 Posters - 3 min pitch)

Computation-In-Memory Based Parallel Adder. Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Razvan Nane, Said Hamdioui and Koen Bertels

Hierarchical Design of Robust and Low Data Dependent FinFET Based SRAM Array. Mohsen Imani, Shruti Patil and Tajana Rosing

Optimal Adiabatic Scaling and the Processor-In-Memory-and-Storage Architecture (OAS+PIMS). Erik Debenedictis, Jeanine Cook, Mark Hoemmen and Tzvetan Metodi

Ex-situ Training of Dense Memristor Crossbar for Neuromorphic Applications. Raqibul Hasan, Chris Yakopcic and Tarek Taha

Defect Tolerance in Diode, FET, and Four-Terminal Switch Based Nano-Crossbar Arrays. Onur Tunali and Mustafa Altun

Fast March Tests for Defects in Resistive Memory. Seyed Nima Mozaffari, Spyros Tragoudas and Themistoklis Haniotakis

Analogue Auto-Associative Memory using a Multi-Valued Memristive Memory Cell. Mohammad Mahmoud A Taha and Wim Jc Melis

Analysis and Design of an Adaptive Proactive Reconfiguration Approach for Memristive Crossbar Memories. Peyman Pouyan, Esteve Amat and Antonio Rubio

Memristor Panic - A Survey of Different Device Models in Crossbar Architectures. Walter Woods, Mohammad Mahmoud A. Taha, Dat Tran, Jens Bürger and Christof Teuscher

Evolution of Radiation-Induced Soft Errors in FinFET SRAMs under Process Variations beyond 22nm. Pablo Royer, Marisa Lopez-Vallejo and Fernando García-Redondo

4:25 - 5:45 PM Poster Session
5:45 PM
End of Technical Session on the First Day
  Day Two

8:15 - 9:05 AM

Breakfast

9:05 AM Session V: Algorithms and CAD
9:05 - 9:35 AM

From Kekule Cells to Molecular Switches. Aaron Germuth and Alex Aravind

9:35 - 9:55 AM

Memristor Crossbar Interconnect Networks. Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui and Koen Bertels

9:55 - 10:25 AM

Automated Synthesis of Crossbars for Nanoscale Computing using Formal Methods. Alvaro Velasquez and Sumit Jha

10:25 AM Session VI: Concept Paper Session B
10:25 - 10:40 AM Defect Consideratons for Robust Sparse Coding Using Memristor Arrays. Patrick Sheridan and Wei Lu
10:40 - 10:55 AM Low-Area Overhead In-situ Training for Memristor-Based Classifier. Elham Zamanidoost, Irina Kataeva and Michael Klachko
10:55 - 11:10 AM Magnetoresistance Implications for Complementary Magnetic Tunnel Junction Logic (CMAT). Joseph S. Friedman, Damien Querlioz and Alan V. Sahakian
11:10 - 11:30 AM Break
11:30 AM Session VII: Approximate Computing at the Nanoscale
11:30 - 12:00 PM Transmission Gate-based Approximate Adders for Inexact Computing. Zhixi Yang, Jie Han and Fabrizio Lombardi
12:00 - 12:30 PM Matrix Multiplication by an Inexact Systolic Array. Fabrizio Lombardi, Ke Chen and Jie Han
12:30 - 1:45 PM Lunch
1:45 PM

Session VIII: Novel Fabric Concepts

1:45 - 2:15 PM

Architecting 3-D Integrated Circuit Fabric with Intrinsic Thermal Management Features. Mostafizur Rahman, Santosh Khasanvis, Jiajun Shi, Mingyu Li and Csaba Andras Moritz

2:15 - 2:45 PM

Full-adder Circuit Design Based on All-spin Logic Device. Qi An, Li Su, Jacques Klein, Sébastien Le Beux, Ian O'Connor and Weisheng Zhao

2:45 - 3:15 PM

Architecting NP-Dynamic Skybridge. Jiajun Shi, Mingyu Li, Mostafizur Rahman, Santosh Khasanvis and Csaba Andras Moritz

3:15 - 3:35 PM

Architecting Connectivity for Fine-grained 3-D Vertically Integrated Circuits. Santosh Khasanvis, Mostafizur Rahman, Mingyu Li, Jiajun Shi and Csaba Andras Moritz

3:35 - 3:55 PM Break
3:55 PM

Session IX: Neuromorphic Systems

3:55 - 4:25 PM

Supervised Learning with Organic Memristor Devices and Prospects for Neural Crossbar Arrays. Christopher Bennett, Damien Querlioz, Jacques-Olivier Klein, Djaafar Chabi, Vincent Derycke, Theo Cabaret and Bruno Jousselme

4:25 - 4:45 PM

Exploiting Local Connectivity of CMOL Architecture for Highly Parallel Orientation Selective Neuromorphic Chips. Melika Payvand and Luke Theogarajan

4:45 - 5:05 PM

On the Impact of OxRAM-based Synapses Variability on Convolutional Neural Networks Performance. Daniele Garbin, Elisa Vianello, Olivier Bichler, Mourad Azzaz, Quentin Rafhay, Philippe Candelier, Christian Gamrat, Gerard Ghibaudo, Barbara De Salvo and Luca Perniola

5:05 -5:25 PM
Closing Remarks
  Day Three
09:00 - 04:00 PM Social Event