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Conference Venue:
Newport Marriott
25 America's Cup Avenue
Newport, Rhode Island,
02840, USA
Phone: +1-401-849-1000

Important Deadlines:

Submission Deadline:
April 15, 2017
April 22, 2017
April 29, 2017

Acceptance Notification:
May 15, 2017
May 31, 2017

Final Version Due:
June 10, 2017

Early Registration:
June 10, 2017

July 25-26, 2017



  Day One

08:00 - 08:45

Registration and Breakfast

08:45 - 09:00

Welcome and Introduction - Lorena Anghel, TIMA Laboratory, Program Chair Nanoarch 2017

09:00 - 10:00


“DARPA Has Seen the Future of Computing … And It’s Analog …” Wired Magazine (PDF Abstract) - Dan Hammerstrom (Bio)

10:00 - 10:15



Session 1: Spintronic & Neural Networks
Moderator: Lorena Anghel, TIMA Laboratory

10:15 - 10:45

A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance. Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Odilia Coi and Pascal Benoit.

10:45 - 11:05

SkyNet: Memristor-based 3D IC for Artificial Neural Networks. Sachin Bhat, Sourabh Kulkarni, Jiajun Shi, Mingyu Li and Csaba Andras Moritz.

11:05 - 11:25

Mixing Circuit based on Neural Associative Memories and Nanoelectronic 1S1R Cells. Arne Heittmann and Tobias G. Noll.

11:25 - 11:45

Spatio-temporal Learning with Arrays of Analog Nanosynapses. Christopher H Bennett, Damien Querlioz and Jacques Olivier-Klein.

11:45 - 13:00


13:00 - 13:30

Session 2: Poster Pitch

Design and Operational Assessment of an Intra-Cell Hybrid L2 Cache. Fabrizio Lombardi, Weiqiang Liu, Jie Han and Linbin Chen.

L^3EP: Low Latency, Low Energy Program-and-Verify for Triple-Level Cell Phase Change Memory. Ali Alsuwaiyan and Kartik Mohanram.

Transient Model with Interchangeability for Dual-Gate Ambipolar CNTFET Logic Design. Xuan Hu and Joseph S. Friedman.

A Compact 8-bit Adder Design using In-Memory Memristive Computing: Towards Solving the Feynman Grand Challenge. Sumit Kumar Jha, Sunny Raj and Dwaipayan Chakraborty.

Automated Synthesis of Compact Multiplier Circuits for in-Memory Computing using ROBDDs. Amad Ul Hassen, Sumit Kumar Jha and Dwaipayan Chakraborty.

Linear Regression based Multi-State Logic Decomposition Approach for Efficient Hardware Implementation. Wafi Danesh and Mostafizur Rahman.

VerilogA Compact Model of a ME-MTJ Based XNOR/NOR Gate. Nishtha Sharma, Andrew Marshall and Jonathan Bird.

13:30 - 14:30 Poster Session
14:30 Session 3: Concept papers I
Session Moderator: Sorin Cotofana, Delft University of Technology
14:30 - 14:45

Memcapacitive Reservoir Computing. Dat Tran and Christof Teuscher.

14:45 - 15:00 CASPER - Configurable Design Space Exploration of Programmable Architectures for Machine Learning using Beyond Moore Devices. Dilip Vasudevan, George Michelogiannakis and David Donofrio.
15:00 - 15:15 Fine-Grained 3D Reconfigurable Computing Fabric with RRAM. Mingyu Li, Jiajun Shi, Sachin Bhat and Csaba Andras Moritz.
15:15 - 15:30 Break
15:30 Session 4: Devices and circuits I
Session Moderator: Santosh Khasanvis, BlueRisc
15:30 - 15:50 Low Cost Multi-Error Correction for 3D Polyhedral Memories. Mihai Lefter, Thomas Marconi, George R. Voicu and Sorin Cotofana.
15:50 - 16:10 Low-Power Multiplexer Designs Using Three-Independent-Gate Field Effect Transistors. Edouard Giacomin, Jorge Romero Gonzalez and Pierre Emmanuel Gaillardon.
Conference dinner
  Day Two
08:00 Breakfast
09:00 Session 5: Spintronic II
Session Moderator: Lorena Anghel, TIMA Laboratory
09:00 - 09:30

A Logic-in-Memory Design with 3-Terminal Magnetic Tunnel Junction Function Evaluators for Convolutional Neural Networks. Sumit Dutta, Saima Siddiqui, Felix Büttner, Luqiao Liu, Caroline Ross and Marc Baldo.

09:30 - 10:00

High Performance and Energy-Efficient In-Memory Computing Architecture based on SOT-MRAM. Zhezhi He, Shaahin Angizi, Farhana Parveen and Deliang Fan.

10:00 - 10:15

Polymorphic Spintronic Logic Gates for Hardware Security Primitives – Device Design and Performance Benchmarking. Shaloo Rakheja and Nickvash Kani.

10:15 - 10:30


10:30 Session 6: Neural networks II
Session Moderator: Fabrizio Lombardi, Northwestern University
10:30 - 10:50 Fully-Connected Single-Layer STT-MTJ-based Spiking Neural Network under Process Variability. Elena Ioana Vatajelu and Lorena Anghel.
10:50 - 11:20 Non-Temporal Logic Performance of an Atomic Switch Network. Kelsey Scharnhorst, Walt Woods, Christof Teuscher, Adam Stieg and James Gimzewski.
11:20 - 11:50 Approximate Vector Matrix Multiplication Implementations for Neuromorphic Applications using Memristive Crossbars. Walt Woods and Christof Teuscher.
11:50 - 12:30 Lunch
12:30 Session 7: Concept papers II
Session Moderator: Rahman Mostafizur, University of Missouri - Kansas City
12:30 - 12:45 Epsilon-greedy Strategy for Online Dicitionary Learning with Realistic Memristor Array Constriants. Fuxi Cai and Wei D. Lu.
12:45-13:00 Hybrid Neural Network using Binary RRAM Devices. Mohammed Zidan, Yeonjoo Jeong and Wei Lu.
13:00-13:15 Naive Bayesian Inference of Handwritten Digits using a Memristive Associative Memory. Mohammad M.A. Taha and Christof Teuscher.

Session 8: Memories
Session Moderator: Sorin Cotofana, Delft University of Technology

13:15 - 13:45

Architecture, Design and Technology Guidelines for Crosspoint Memories. Alexandre Levisse, Pablo Royer, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau and Jean-Michel Portal.

13:45 - 14:15

Ultra High Density 3D SRAM Cell Design in Stacked Horizontal Nanowire (SN3D) Fabric. Naveen Kumar Macha, Sandeep Geedipally and Mostafizur Rahman.

14:15 - 14:30



Session 9: Devices and circuits II
Session Moderator: Csaba Andras Moritz, University of Massachussets Amherst

14:30 - 14:50

AOI-Based Data-Centric Circuits for Near-Memory Processing. Fabrizio Lombardi and Salin Junsangsri.

14:50 - 15:20

Power-Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS. Jiajun Shi, Mingyu Li and Csaba Andras Moritz.

15:20 - 15:50

Energy Efficient Computation using Injection Locked Bias-Field Free Spin-Hall Nano-Oscillator Array with Shared Heavy Metal. Karthik Yogendra, Minsuk Koo and Kaushik Roy.

15:50 - 16:20

A self-calibrating sense amplifier fora true random number generator using hybrid FinFET-Straintronic MTJ. Sudipta Bhuin, Joseph Sweeney, Samuel Pagliarini, Ayan Biswas and Lawrence Pileggi.

16:20 - 16:25

Closing - Csaba Andras Moritz, University of Massachussets Amherst