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2nd IEEE International Workshop on
Defect and Fault Tolerant Nanoscale Architectures
(NANOARCH 2006) To be held in conjunction with the International Symposium on Computer Architecture June 17, 2006 Boston Park Plaza Hotel, Boston, MA, USA | |||||||||||||||||
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Nanoarch 2007 Nanoarch 2005 Call for Papers Home Sign In GENERAL CHAIR R Karri, Polytechnic U PROGRAM CHAIR A Orailoglu, UC San Diego SPECIAL ISSUE CO-CHAIRS M. Stan, U Virginia K. Likharev, Stony Brook SPECIAL SESSIONS CHAIR Dan Hammerstrom, Portland State PUBLICITY C0-CHAIRS J. Chen, National Institute of Nanotechnology & U Alberta S. Levitan, U. Pittsburgh INDUSTRY LIAISON W. Joyner, SRC NANO TC LIAISON R Kapur, Synopsys ASIAN LIAISON K Kim, Incheon PUBLICATIONS CHAIR D. Sorin, Duke E-MEDIA CHAIR I Bayraktaroglu, Sun PROGRAM COMMITTEE Iris Bahar, Brown Valeriu Beiu, Washington State Shamik. Das, MITRE Andre DeHon, Caltech Chris Dwyer, Duke James Ellenbogen, MITRE Jose Fortes, Univ of Florida Haldun Hadimioglu, Polytechnic Niraj Jha, Princeton Alexander Khitun, UCLA Yusuf Leblebici, EPFL Meyya Meyyappan, NASA Ames Kaushik Roy, Purdue Alberto Sangiovanni-Vincentelli, UCB Sandeep Shukla, Virginia Tech Kang Wang, UC Los Angeles Kaijie Wu, UIC |
WELCOME MESSAGEWelcome to the Second IEEE International Workshop on Defect-Tolerant Nanoscale Architectures (NANOARCH'06). We envision this NANOARCH to evolve into a forum for all aspects of emerging nanoscale architectures: defect and fault tolerant architectures, emerging computational paradigms for nanoelectronics, modeling and simulation of novel nanoelectronic architectures and concepts, micro-architectural concepts using nanoarchitectural building blocks, dynamic reconfiguration in nanoelectronic architectures, defect and fault models in emerging nanoelectronic device technologies, manufacture testing methodologies for nanoelectronic architectures, yield models, yield analysis and yield enhancement in nanoelectronics, CAD of defect and fault-tolerant nanoelectronic architectures. The NANOARCH'06 workshop received 31 paper proposals by the abstract deadline and 24 full submissions by the final submission deadline. The program committee conducted a rigorous review process, with each paper receiving at least 5 reviews. Several of the papers received 6 reviews. Based on the comments of the reviewers and the subsequent deliberations of the program committee, we were able to put together an excellent program composed of 7 long paper presentations and 4 short paper presentations, resulting in an acceptance rate of 35.5%. The 7 long papers represent the cross section of the best in the area of nanoscale memory and computing architectures and design methods with a 22.6% acceptance ratio. Some of the accepted papers will be included in a special issue of IEEE Transactions on Nanotechnology. In addition, we are fortunate that Prof. Alain Kaloyeros, President, Albany NanoTech and Chief Administrative Office, College of Nanoscale Science and Engineering, SUNY Albany has agreed to give the keynote. We would like to thank all members of the program and organizing committee and acknowledge their selfless dedication in helping us in the difficult task of selecting among a set of excellent paper proposals. Most importantly, we would like to thank all of you, the NANOARCH'06 participants, the NANOARCH'06 paper submitters and session chairs, for making NANOARCH a success and establishing it as the pre-eminent forum for exchange of innovative ideas in nanoelectronic architectures and systems. We would like to thank NSF for supporting graduate student travel grants to NANOARCH.
We wish you all a productive time in Boston and hope that you will continue to make NANOARCH a success by actively participating in it, assisting in its organization, and letting us always know when we can do something better. Thank you all for coming.
Program
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