The evolving landscape of wireline signaling has reached an exciting point after decades of evolution. This talk aims to walk through this journey, reflect on the learnings, and find a way towards 200+ Gb/s signaling techniques. In the first decade of high-speed signaling, data rates increased from 1 Gb/s to 28 Gb/s, consistently and on a relatively predictable path by adopting equalization and making them more affordable through CMOS scaling. Most of the research effort was towards optimizing link performance in a strict power budget limited scenario. As we enter the 50+ Gb/s main challenge, we maximize the Signal-to-Noise Ratio (SNR) for a given transmit power with multilevel signaling. Fortunately, digital signal processing and coding have helped us to go beyond 100 Gb/s. The talk will conclude with potential future directions to break the barrier beyond 250 Gb/s electrical signaling.
Time: November 9, 10:00 am EST (UTC-5:00)
Short Bio: Masum Hossain received the M.Sc. degree from Queen’s University, Kingston, ON, Canada, in 2005, and the Ph.D. degree from the University of Toronto, Toronto, ON, in 2010. From 2008 to 2010, he was with the Analog and Mixed-Signal Division, Gennum Corporation, Burlington, ON, where he was involved in developing the world’s highest-capacity and most power-efficient cross-point router solution. He was a Senior Member of Technical Staff with the Rambus Laboratory, Sunnyvale, CA, USA, where he was involved in advanced equalization and clock-recovery techniques for interfaces. In 2013, he joined the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada, where he is currently an Associate Professor. Dr. Hossain was a recipient of the Best Student Paper Award at the 2008 IEEE Custom Integrated Circuits Conference and the Analog Device’s Outstanding Student Designer Award in 2010. In 2016, he received the Rambus’s distinguished inventor award for 20 unique patents.
Several recent studies have demonstrated the usability of emerging technology devices in Neural Network hardware designs. Most works report that the emerging memory devices are ideal candidates for synaptic weight implementations, but also in some cases they have been shown to have good potential also for neuron (processing unit) implementations. Current emerging-technology-based neural networks are able to store reduced-precision numbers for weights. However, to achieve better convergence and speed of the learning and inference process for intensive computing applications, the neural network has to be designed with a quite high degree of redundancy. Moreover, the architecture will also have to mitigate the inherent high variability of the emerging technologies. The Ensemble Neural Networks paradigm allows building more power-efficient and accurate neural networks, by combining predictions for multiple, different neural networks models to reduce variance, minimize errors and improve accuracy. This talk addresses opportunities and challenges of binarized Ensemble Neural Networks with spintronic devices.
Chiplet-based integration is a paradigm shift that shapes the way we design our future systems. The concept is to move forward from large systems-on-chip that are limited by communication, thermal design power, and reticle size, toward a robust plug-and-play approach, where small, hardened IP heterogeneous off-the-shelf chiplets are seamlessly integrated on a single platform. In this talk, we will discuss the current state-of-the-art and challenges in chiplet integration, and specifically examine an ultra-large wafer-scale platform for applications, such as artificial intelligence acceleration, high-performance computing, and neuromorphic hardware.
Nonvolatile storage devices, called "magnetic tunnel junction (MTJ)" devices, have potential advantages such as fast read/write, and high endurance, together with back-end-of-the-line compatibility, which could offer the potential advantages to break through the performance bottleneck in the present era of CMOS-based VLSI circuits and systems. In this presentation, some concrete examples based on MTJ-based logic-in-memory architectures are presented and their suitability for Internet-of-Things (IoT) applications are discussed.
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