16th IEEE / ACM International Symposium on Nanoscale Architectures

November 8-10, 2021, Virtual

News

About NANOARCH 2021

NANOARCH is the annual cross-disciplinary forum for the discussion of novel post-CMOS and advanced nanoscale CMOS directions. The symposium seeks papers on innovative ideas for solutions to the principal challenge faced by integrated electronics in the 21st century: How to design, fabricate, and integrate nanosystems to overcome the fundamental CMOS limitations? In particular, such systems could:

  •  Contain unconventional nanodevices with unique capabilities, e.g., beyond simple switch behavior
  •  Introduce new logic and memory concepts
  •  Involve novel circuit styles
  •  Introduce new computing concepts
  •  Explore security architectures with nanotechnology
  •  Reconfigure and/or mask faults at much higher rates than in CMOS
  •  Require design tools and methodologies fundamental rethinking

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ACM
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Call for Papers


This 16th symposium aims to incorporate several exciting sessions on emerging computing paradigms (e.g., approximate, quantum, neuromorphic, molecular, spintronic), novel nano-based computing architectures, 2D materials (e.g., graphene) nanoelectronics and computing, beyond charge-based computing, emerging memory devices and in memory computing, nanoelectronics for biomedical systems, and to provide extended opportunities for interaction among the participants. In addition to 6-page length Regular Papers, we also invite 2-page Concept Papers presenting less developed but radical and highly innovative work in the area of nanofabrication, nanocomputing, and emerging nanosystem application.

NANOARCH 2021 topics of interest (both theoretical and experimental) include (but are not limited to):

  •  Novel nanodevices and manufacturing/integration ideas with a focus on nanoarchitectures
  •  Nanoelectronic circuits, nanofabrics, computing paradigms and nanoarchitectures
  •  Future and emergent nano-computing paradigms, e.g., approximate, quantum, neuromorphic, molecular, spintronic
  •  Paradigms and nanoarchitectures for computing with unpredictable devices
  •  Emerging memory nano-devices and in memory computing nano-architectures
  •  Security architectures with nanofabrics
  •  Reliability aware computing
  •  2D/3D, hybrid, defect/fault tolerant architecture, integration, and manufacturing
  •  Nanodevice and nanocircuit models, methodologies and computer aided design tools
  •  Fundamental limits of computing at the nanoscale


Significant Dates

Special Session Proposals due: August 22nd August 29th, 2021

Special Session Notification of Acceptance: August 29th September 5th, 2021

Regular / Special Session Paper Submission: August 22nd August 29th, 2021

Acceptance Notification: September 24th, 2021

Final Version: October 5th, 2021

Special Session Call


The NANOARCH 2021 technical program will include Special Sessions. Their objective is to complement the regular program with new or emerging topics that are of particular interest to practitioners and experts for highest performance at nanoscale architectures that may also cut across and beyond disciplines traditionally represented at NANOARCH.

We recall that, typically, each Special Session comprises at least 4 presentations. Prospective organizers of Special Sessions should submit proposals delivering the following:

  • Topic Title (approx. 10 words)
  • Organizers Name and Affiliation
  • Session Rationale and Outline (approx. 500 words); the rationale should stress the novelty of the topic and/or its multidisciplinary features (if any)
  • Session Paper List (min. 4 papers without more than 2 per involved research group) including the author(s) affiliation(s), paper title and abstract (approx. 100-200 words)

Proposals will be evaluated based on the timeliness of the topic, and the qualifications of organizers and contributors.

After Special Session proposals are approved, manuscripts may be submitted to the special session and should conform to the formatting and electronic submission guidelines of regular NANOARCH papers. The invited papers, which are part of accepted special sessions proposals, will undergo the same review process as Regular and Concept papers. If, at the end of the review process, three (3) or less papers are accepted, the special session will be cancelled and the accepted papers will be moved to regular sessions.

Proposals should be sent via e-mail to the Special Session Chairs by August 22nd August 29th, 2021 at the latest.
Notification of Acceptance: August 29th September 5th, 2021.

Submission Guidelines


Authors are invited to submit of up to 6 pages in length for the Regular Paper Sessions and Special Sessions and 2 pages in length for the Concept Paper Sessions in PDF version, double column with a minimum font size of 10 points on the symposium submission website (EasyChair). Author may choose to make submissions anonymous, although that is not mandatory. The electronic submission will be considered evidence that upon acceptance, the author(s) will present their paper at the symposium. Accepted and presented papers will be submitted for inclusion to IEEE Xplore and ACM Digital Library. All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript of novel unpublished work (not to exceed 6 pages of single spaced text, including figures and tables).

Papers must be in the formats described on submissions guidelines and using the IEEE templates that you can find at:
IEEE Manuscript Templates for Conference Proceedings

Accepted and Presented papers will be considered for NANOARCH Best Paper Award, and the conference content will be submitted for inclusion into IEEE Xplore and ACM Digital Library as well as other Abstracting and Indexing (A&I) databases.

After the conference, authors are invited to submit extended paper versions (containing at least 30% but preferably 50% new material), to pass the normal review process, for potential publication in an IEEE Transactions on Nanotechnology NANOARCH 2021 Special issue.

Registration

To be announced


Technical Committee

Pierre Boulet, University Lille 1, France

Ramon Canal, Universitat Politecnica de Catalunya, Spain

Joseph Friedman, The University of Texas at Dallas, USA

Vincent Gaudet, University of Waterloo, Canada

Swaroop Ghosh, The Pennsylvania Stat University, USA

Jingtong Hu, University of Pittsburgh, USA

Li Jiang, Shanghai Jiao Tong University, China

Xueqing Li, Tsinghua University, China

Weiqiang Liu, Nanjing University of Aeronautics and Astronautics, China

Fabrizio Lombardi, Northeastern University, USA

Marisa Lopez-Vallejo, Universidad Politecnica de Madrid, Spain

Anca Molnos, CEA-LETI, France

Kundan Nepal, University of St Thomas, USA

Tianxiao Nie, Beihang University, China

Ian O'Connor, Lyon Institute of Nanotechnology, France

Naoya Onizawa, Tohoku University, Sendai, Japan

Alexandru Paler, Johannes Kepler University Linz, Austria

Antonio Rubio, Universitat Politecnica de Catalunya, Spain

Liang Shi, East China Normal University, China

Ronald Tetzlaff, Technische Universität Dresden, Germany

Christof Teuscher, Portland State University, USA

Amit Trivedi, University of Illinois at Chicago, USA

Ioannis Vourkas, Universidad Tecnica Federico Santa Maria, Chile

Lan Wei, University of Waterloo, Canada

Wu Xiulong, Anhui University, China

Lang Zeng, Beihang University, China

Yue Zhang, Beihang University, China

Conference Time-schedule

Keynote Speakers

Lorena Anghel (Grenoble INP, Grenoble, France)

"Ensemble Neural Networks with Spintronic Devices - Opportunities and Challenges"

Lorena Anghel Several recent studies have demonstrated the usability of emerging technology devices in Neural Network hardware designs. Most works report that the emerging memory devices are ideal candidates for synaptic weight implementations, but also in some cases they have been shown to have good potential also for neuron (processing unit) implementations. Current emerging-technology-based neural networks are able to store reduced-precision numbers for weights. However, to achieve better convergence and speed of the learning and inference process for intensive computing applications, the neural network has to be designed with a quite high degree of redundancy. Moreover, the architecture will also have to mitigate the inherent high variability of the emerging technologies. The Ensemble Neural Networks paradigm allows building more power-efficient and accurate neural networks, by combining predictions for multiple, different neural networks models to reduce variance, minimize errors and improve accuracy. This talk addresses opportunities and challenges of binarized Ensemble Neural Networks with spintronic devices.

Time: November 8, 8:00 am EST (UTC-5:00)

Short Bio: Lorena Anghel received her PhD in 2000 from Grenoble Institute of Engineering and Management (INPG). Currently she is Full Professor at INPG in Microelectronics and Embedded Systems Engineering and member of the research staff of SPINTEC Laboratory. Her research interests include: design and validation of reliable digital integrated circuits, hardware/software tolerant design, aging induced reliability issues, defects and variation tolerance for emerging technologies, with a particular focus on design of logic and memory circuits based on magnetic components. Since 2019 she has been holding an Excellence Chair position at the AI Multi-Disciplinary Institute in Grenoble on the topic of “Non Volatile Emerging based Spiking Neural Network”. She was General Chair of IEEE VLSI Test Symposium in 2020 and 2021, IEEE European Test Symposium in 2012 and IEEE On-Line Test Symposium in 2005, and Program Chair of IEEE VLSI Test Symposium in 2015 and 2016, DCIS Conference in 2008 and 2009, founder of SERESSA Summer School from 2006 to 2008. Dr. Anghel has been recipient of 5 Best Paper Awards and one Outstanding Paper Award. From 2016 to 2020, Dr. Anghel was Deputy Vice President at INPG, in charge of Industrial Relationships. She is currently Scientific Director of INPG covering the following topics: Micro and Nanoelectronic Technology and Design, Computer Science and Informatics.

Boris Vaisband (McGill University, Montreal, QC, Canada)

"Chiplet-Based Heterogeneous Integration"

Boris Vaisband Chiplet-based integration is a paradigm shift that shapes the way we design our future systems. The concept is to move forward from large systems-on-chip that are limited by communication, thermal design power, and reticle size, toward a robust plug-and-play approach, where small, hardened IP heterogeneous off-the-shelf chiplets are seamlessly integrated on a single platform. In this talk, we will discuss the current state-of-the-art and challenges in chiplet integration, and specifically examine an ultra-large wafer-scale platform for applications, such as artificial intelligence acceleration, high-performance computing, and neuromorphic hardware.

Time: November 8, 11:00 am EST (UTC-5:00)

Short Bio: Boris Vaisband is an Assistant Professor in the Department of Electrical and Computer Engineering at McGill University in Montreal, QC, Canada. His current research interests are in integration and design methodologies for heterogeneous systems, including power delivery, communication, thermal aware design and floorplanning, and testing. Some applications of interest are ultra-large-scale artificial intelligence systems, high performance computing, hardware obfuscation, Internet of Things, and bio-compatible devices.

Masum Hossain (University of Alberta, Edmonton, AB, Canada)

"High-Speed Signaling for Next-Generation Data Centers"

Masum Hossain The evolving landscape of wireline signaling has reached an exciting point after decades of evolution. This talk aims to walk through this journey, reflect on the learnings, and find a way towards 200+ Gb/s signaling techniques. In the first decade of high-speed signaling, data rates increased from 1 Gb/s to 28 Gb/s, consistently and on a relatively predictable path by adopting equalization and making them more affordable through CMOS scaling. Most of the research effort was towards optimizing link performance in a strict power budget limited scenario. As we enter the 50+ Gb/s main challenge, we maximize the Signal-to-Noise Ratio (SNR) for a given transmit power with multilevel signaling. Fortunately, digital signal processing and coding have helped us to go beyond 100 Gb/s. The talk will conclude with potential future directions to break the barrier beyond 250 Gb/s electrical signaling.

Time: November 9, 10:00 am EST (UTC-5:00)

Short Bio: Masum Hossain received the M.Sc. degree from Queen’s University, Kingston, ON, Canada, in 2005, and the Ph.D. degree from the University of Toronto, Toronto, ON, in 2010. From 2008 to 2010, he was with the Analog and Mixed-Signal Division, Gennum Corporation, Burlington, ON, where he was involved in developing the world’s highest-capacity and most power-efficient cross-point router solution. He was a Senior Member of Technical Staff with the Rambus Laboratory, Sunnyvale, CA, USA, where he was involved in advanced equalization and clock-recovery techniques for interfaces. In 2013, he joined the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada, where he is currently an Associate Professor. Dr. Hossain was a recipient of the Best Student Paper Award at the 2008 IEEE Custom Integrated Circuits Conference and the Analog Device’s Outstanding Student Designer Award in 2010. In 2016, he received the Rambus’s distinguished inventor award for 20 unique patents.

Takahiro Hanyu (Tohoku University, Sendai, Japan)

"Challenge of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications"

Takahiro Hanyu Nonvolatile storage devices, called "magnetic tunnel junction (MTJ)" devices, have potential advantages such as fast read/write, and high endurance, together with back-end-of-the-line compatibility, which could offer the potential advantages to break through the performance bottleneck in the present era of CMOS-based VLSI circuits and systems. In this presentation, some concrete examples based on MTJ-based logic-in-memory architectures are presented and their suitability for Internet-of-Things (IoT) applications are discussed.

Time: November 10, 8:00 am EST (UTC-5:00)

Short Bio: Takahiro Hanyu received the B.E., M.E. and D.E. degrees in Electronic Engineering from Tohoku University, Sendai, Japan, in 1984, 1986 and 1989, respectively. He is currently a Professor and Education/Research Councillor (April 2018 to present) in the Research Institute of Electrical Communication (RIEC), Tohoku University. His general research interests include nonvolatile logic circuits and their applications to ultra-low-power and/or highly dependable VLSI processors, and post-binary computing and its application to brain-inspired VLSI systems.

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