Related
Conferences 
Important Deadlines:
Submission
Deadline:
April 10, 2011
Acceptance
Notification:
May 5, 2011
Final
Version Due:
May 21, 2011
Early
Registration:
May 9, 2011
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NANOARCH 2011
Advance Program Wednesday June 8th |
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| 8:00 AM | Breakfast | |
| 8:30 AM | Introduction | C.A. Moritz, K. Wang, I. O'Connor |
| 8:45 AM | Keynote | |
| C.Y Sung Ph.D, Nanoelectronics Program Manager | ||
| Science and Technology Strategy Department, IBM T.J. Watson Research Center | ||
| 9:30 AM | Session I - Reconfigurable nanocomputing | |
| Chair: Christof Teuscher, Portland State University, USA | ||
9:30-10:00 |
A Novel FPGA Architecture with Memristor-Based Reconfiguration | |
Jason Cong, Bingjun Xiao|
| | |
| UCLA, Department of Computer Science, Los Angeles, CA, USA | ||
| 10:00-10:30 | Ultra-Fine Grain FPGAs: A Granularity Study | |
Pierre-Emmanuel Gaillardon, M. Haykel Ben-Jamaa, Fabien Clermidy, Ian O’Connor|
| | |
| CEA-LETI, DACLE, Grenoble, France | ||
| 10:30 AM | Break | |
| 11:00 AM | Session II - Crosscuts | |
| Chair: Helen Li, Polytechnic Institute Of New York University, USA | ||
| 11:00-11:30 | A Hybrid Memory Cell Using Single-Electron Transfer | |
| Wei Wei, Jie Han, and Fabrizio Lombardi | ||
| Northeastern University, Dept of ECE, Boston, MA, USA | ||
| 11:30-12:00 | Inexact Computing for Ultra Low-Power Nanometer Digital Circuit Design | |
| Jaeyoon Kim and Sandip Tiwari | ||
| Cornell University, Electrical and Computer Engineering, Ithaca, NY, USA | ||
| 12:00-12:15 | Scalability and Design-Space Analysis of a 1T-1MTJ Memory Cell | |
| Richard Dorrance, Fengbo Ren, Yuta Toriyama, Amr Amin, C.-K. Ken Yang, Dejan Markovic | ||
| UCLA, Electrical Engineering, Los Angeles, CA, USA | ||
| 12:15-12:30 | Improving speed of operation of NEM relay logic circuits using distributed charge-boosting | |
| Ramakrishnan Venkatasubramanian, Sujan K. Manohar, Poras T. Balsara | ||
| University of Texas at Dallas, Electrical Engineering, Richardson, TX, USA | ||
| 12:30 PM | Lunch | |
| 1:45 PM | Session III - Memories | |
| Chair: Fabrizio Lombardi, Northeastern University, USA | ||
| 1:45-2:15 | Variation-Tolerant Ultra Low-Power Heterojunction Tunnel FET SRAM Design | |
| Vinay Saripalli, Jaydeep P. Kulkarni, Suman Datta, Vijaykrishnan Narayanan | ||
| Pennsylvania State University, Computer Science and Engineering, University Park, PA, USA | ||
| 2:15-2:45 | Analysis of STT-RAM Cell Design with Multiple MJTs Per Access | |
| Henry Park, Richard Dorrance, Amr Amin, Fengbo Ren, C.K. Ken Yang, Dejan Markovic | ||
| UCLA, Electrical Engineering, Los Angeles, CA, USA | ||
| 2:45-3:00 | 3D-HIM: A 3D High-density Interleaved Memory for Bipolar RRAM Design | |
| Yi-Chung Chen, Hai Li, Wei Zhang, Robinson E. Pino | ||
| Polytechnic Institute Of New York University, ECE, Brooklyn, New York, NY, USA | ||
| 3:00-3:15 | Using OxRRAM Memories for Improving Communications of Reconfigurable FPGA Architectures | |
| Santhosh Onkaraiah, Pierre-Emmanuel Gaillardon, Marina Reyboz, Fabien Clermidy,Jean-Michel Portal, Marc Bocquet, Christophe Muller | ||
| CEA-LETI, DCOS, Grenoble, France | ||
| 3:15 PM | Poster session I | |
| 3:15-3:20 | Regular 2D Nasic-based Architecture and Design Space Exploration | |
| Ciprian Teodorov, Pritish Narayanan, Loic Lagadec, Catherine Dezan | ||
| Université de Bretagne Occidentale, Brest, France | ||
| 3:20-3:25 | Self-Timed Nano-PLA | |
| Masoud Zamani, Mehdi B. Tahoori | ||
| Northeastern University, ECE, Boston, MA, US | ||
| 3:25-3:30 | Graphene Nanoribbon Crossbar Nanomesh | |
| K. M. M. Habib, A. Khitun, A. A. Balandin, and R. K. Lake | ||
| University of California Riverside, Electrical Engineering, Riverside, CA, U.S.A. | ||
| 3:30-3:35 | Nanofabric Power Analysis: Biosequence Alignment Case of Study | |
| Stefano Frache, Luca Gaetano Amaru', Mariagrazia Graziano and Maurizio Zamboni | ||
| Politecnico di Torino, Electronics Dept., Torino, Italy | ||
| 3:45 PM | Break | |
| 4:15 PM | Session IV - Nanofabric updates | |
| Chair: Ian O'Connor, Lyon Institute of Nanotechnology, France | ||
| 4:15-4:45 | Nanoscale Application Specific Integrated Circuits | |
| Pritish Narayanan, Jorge Kina, Pavan Panchapakeshan, Priyamvada Vijayakumar, Kyeong-Sik Shin, Mostafizur Rahman, Michael Leuchtenburg, Israel Koren, Chi On Chui and Csaba Andras Moritz | ||
| University of Massachusetts Amherst, Electrical and Computer Engg., Amherst, MA, USA | ||
| 4:45-5:15 | Spin Wave Functions Nanofabric Update | |
| Prasad Shabadi, Alexander Khitun, Kin Wong, P. Khalili Amiri, Kang L. Wang and C. Andras Moritz | ||
| University of Massachusetts, ECE, Amherst, MA, USA | ||
| 5:15 PM | End of first day | |
|
Thursday June 9th |
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| 8:00 AM | Coffee | |
| 8:30 AM | Session V - Energy and power efficiency | |
| Chair: Sorin Cotofana, Delft University of Technology, Netherlands | ||
| 8:30-9:00 | Power Efficient Nanophotonic on-Chip Network for Future Large Scale Multiprocessor Architectures | |
| Somayyeh Koohi, Shaahin Hessabi | ||
| UC Davis, Computer Engineering Department, Davis, CA, United States | ||
| 9:00-9:30 | Energy Efficient Many-core Processor for Recognition and Mining using Spin-based Memory | |
| Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Anand Raghunathan, and Kaushik Roy | ||
| Purdue University, Electrical Eng, West Lafayette, IN, USA | ||
| 9:30-10:00 | Low-Power Functionality Enhanced Computation Architecture using Spin-Based Devices | |
| C. Augustine, G. Panagopoulos, B. Behin-Aein, S. Srinivasan, A. Sarkar and Kaushik Roy | ||
| Purdue University, ECE, West Lafayette, IN, USA | ||
| 10:15 AM | Poster session II | |
| 10:15-10:20 | Robust Neural Logic Block (NLB) based on Memristor Crossbar Array | |
| Djaafar Chabi, Weisheng Zhao, Damien Querlioz, Jacques-Olivier Klein | ||
| Université Paris Sud, Institut d'Electronique Fondamentale, Bures-sur-Yvette, France | ||
| 10:20-10:25 | A Scheme for Computation in Nanoscale Dynamical Systems: Gated Discrete Phase-Shift Interactions | |
| Paul M. Riechers and Richard A. Kiehl | ||
| UC Davis, Electrical & Computer Engineering, Davis, CA, USA | ||
| 10:25-10:30 | Learning with memristive devices: how should we model their behavior? | |
| Damien Querlioz, Philippe Dollfus, Olivier Bichler, Christian Gamrat | ||
| Université Paris-Sud, Institut d'Electronique Fondamentale, Orsay, France | ||
| 10:30-10:35 | Performance Assessment of Partially Unizpped Carbon Nanotube Field-Effect Transistors | |
| Youngki Yoon, Sayeef Salahuddin | ||
| University of California at Berkeley, EECS, Berkeley, CA, USA | ||
| 10:45 AM | Break | |
| 11:00 AM | Session VI - Methods, models and tools | |
| Chair: Shamik Das, MITRE Corporation, USA | ||
| 11:00-11:30 | Ambipolar double-gate FET binary-decision diagram (Am-BDD) for reconfigurable logic cells | |
| K. Jabeur, N. Yakymets, I. O'Connor, S. Le Beux | ||
| Ecole Centrale de Lyon, Lyon Institute of Nanotechnology, France | ||
| 11:30-11:45 | Fundamental Lower Bounds on Heat Dissipation for Transistor-Based Nanocomputing Paradigms | |
| Ilke Ercan, Mostafizur Rahman and Neal G. Anderson | ||
| University of Massachusetts, Electrical Engineering, Amherst, USA | ||
| 11:45-12:00 | A Unified Aging Model of NBTI and HCI Degradation towards Lifetime Reliability Management for Nanoscale MOSFET Circuits | |
| Yao Wang, Sorin Cotofana and Liang Fang | ||
| Delft University of Technology, Computer Engineering Laboratory, Delft, Netherlands | ||
| 12:00-12:15 | Impact of Nanomanufacturing Flow on Systematic Yield Losses in Nanoscale Fabrics | |
| Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna and Csaba Andras Moritz | ||
| University of Massachusetts, ECE, Amherst, MA, USA | ||
| 12:15 PM | Own lunch | |
| 1:45 PM | Session VII - Hybrid systems | |
| Chair: Fabien Clermidy, CEA-LETI, France | ||
| 1:45-2:15 | Hybrid Graphene Nanoribbon-CMOS Tunneling Volatile Memory Fabric | |
| Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake and Csaba Andras Moritz | ||
| University of Massachusetts, ECE, Amherst, MA, USA | ||
| 2:15-2:45 | N3ASICs: Designing Nanofabrics with Fine-Grained CMOS Integration | |
| Pavan Panchapakeshan, Pritish Narayanan and Csaba Andras Moritz | ||
| University of Massachusetts, ECE, Amherst, MA, USA | ||
| 2:45-3:00 | Towards ”Zero-energy” using NEMFET-based Power Management for 3D Hybrid ICs | |
| George Razvan Voicu, Marius Enachescu, Sorin Dan Cotofana | ||
| TU Delft, CE, Delft, Netherlands | ||
| 3:00-3:15 | NEMTronics: Symbiotic Integration of Nanoelectronic and Nanomechanical Devices for Energy-Efficient Adaptive Computing | |
| Xinmu Wang, Seetharam Narasimhan, and Swarup Bhunia | ||
| Case Western Reserve U., EECS, Cleveland, OH, USA | ||
| 3:15-3:30 | NEMS based Thermal Management for 3D Many-core System | |
| Xiwei Huang, Hao Yu, Wei Zhang | ||
| Nanyang Technological University, EEE, Singapore, Singapore | ||
| 3:30 PM | Break | |
| 3:45 PM | NanoArch 2012: Panel and closing remarks | |
| 4:15 PM | End of technical program | |
| 6:30 PM | Social Event: Cruise in San Diego Bay | |
| 7:00 PM | Dinner, best paper awards | |
| 10:00 PM | Return to hotel |