NANOARCH 2008

		Technical Program
		Day 1: Thursday, June 12, 2008


	Time	Sessions
	07:30 – 08:00	Breakfast
	08:00 – 08:15	Opening Remarks (Program and General Chairs)
	08:15 – 09:45	Invited Session: Future of Nanocomputing: A Few Emerging Technologies Session Chair: Dwarup Bhunia, Case Westerrn Reserve U Hybrid CMOS/Nanoelectronic Circuits: Opportunities and Challenges Konstantin K. Likharev, State University of New York at Stony Brook, Stony Brook Nanocomputer Systems R&D at The MITRE Corporation Shamik Das, The MITRE Corporation, McLean, VA, USA Designing Noise-Tolerant Logic Circuits Based on Probabilistic Computation Iris Bahar, Brown University, Providence
	09:45 – 10:00	Break
	10:00 – 11:20	Session 1: System Level Issues in Nanoarchitectures Session Chair: Ryan Kastner, UC San Diego System Level Performance Analysis of Carbon Nanotube Global Interconnects for Emerging Chip Multiprocessors Sudeep Pasricha, Nikil Dutt and Fadi J. Kurdahi Online Test and Fault-Tolerance for Nanoelectronic Programmable Logic Arrays Saturnino Garcia and Alex Orailoglu Assessing Random Dynamical Network Architectures for Nanoelectronics (Short Paper) Christof Teuscher, Natali Gulbahce and Thimo Rohlf
	11:20 – 11:30	Break
	11:30 – 12:30	Keynote (Open to all DAC participants): The Impact of Memristance and Memristors in Nanoelectronic Circuits Dr. R. Stanley Williams Hewlett-Packard Labs, Palo Alto, CA
	12:30 – 14:00	Lunch Break
	14:00 – 15:20	Session 2: High Level Defect Tolerance in Nanoelectronics Session Chair: Mohammad Tehranipoor, U Connecticut Locality Aware Redundancy Allocation in Nanoelectronic Systems Wenjing Rao, Alex Orailoglu and Keith Marzullo A DSP Nanosystem with Defect Tolerance Weiguo Tang and Lei Wang A Voterless Strategy for Defect-Tolerant Nano-Architectures (Short Paper) A. Namazi, M. Nourani and M. Saquib
	15:20 – 15:30	Break
	15:30 – 16:00	Poster Session I
	16:00 – 17:30	Panel: Non-CMOS NanoElectronics — Will it ever be Real? Session Chair: Paul Franzon, NCSU Organizer/Moderator: Dr. Paul D. Franzon, N. C. State, Raleigh, NC Panelists: Pinaki Mazumder, NSF Kaustav Banerjee, UCSB Sadas Shankar, Intel Konstantin Likharev, Suny Stoneybrook Paul Franzon, NCSU
	18:00	Social Program

		Day 2: Friday, June 13, 2008

	Time	Sessions
	08:00 – 08:30	Breakfast
	08:30 – 09:30	Special Session Nanomemory Technologies in Industry Session Chair: Shamik Das, MITRE Nanocrystals: From Physics to Memory Technology Dr. Muralidhar Ramachandran, Freescale Semiconductor Phase Change Materials and Their Application to Phase Change Random Access Memory Dr. Simone Raoux, IBM Almaden Research Center
	09:30 – 09:50	Break
	09:50 – 11:10	Session 3: Reconfigurability Challenges and Applications Session Chair: Igor Markov, U Michigan Defect Tolerance in QCA-Based PLAs Michael Crocker, X. Sharon Hu and Michael Niemier On Brain-Inspired Connectivity and Hybrid Network Topologies Basheer A. M. Madappuram, Valeriu Beiu and Martin McGinnity Reconfigurable BDD Based Quantum Circuits (Short Paper) Soumya Eachempati, Vinay Saripalli, N. Vijaykrishnan and Suman Datta
	11:10 – 11:30	Break
	11:30 – 12:30	Keynote (Open to all DAC participants): Ultra-high Density Electronic Circuitry: Applications and Fundamental Opportunities Dr. James R. Heath Elizabeth W. Gilloon Professor and Professor of Chemistry California Institute of Technology, CA
	12:30 – 14:00	Lunch
	14:00 – 14:30	Poster Session II
	14:30 – 14:40	Break
	14:40 – 16:30	Session 4: Device Architectures in Nanoelectronics Session Chair: Yiorgos Makris, Yale University Single Electron Tunneling Delay Insensitive and Fluctuation Based Computation Paradigms and Circuits Saleh Safiruddin, Sorin Dan Cotofana and Ferdinand Peper Evaluation of Multiple Supply and Threshold Voltages for Low-Power FinFET Circuit Synthesis Prateek Mishra, Anish Muttreja and Niraj K. Jha Spike-Timing-Dependent Learning in Memristive Nanodevices Greg S. Snider rFPGA: CMOS-Nano Hybrid FPGA Using RRAM Components (Short Paper) Ming Liu and Wei Wang
	16:30	Closing Remarks

Day 2: Friday, June 13, 2008