17th ACM International Symposium on Nanoscale Architectures

December 7-9, 2022 (Virtual)


Registration is open! Authors MUST get registered until Nov 27, 2022.

About NANOARCH 2022

NANOARCH is the annual cross-disciplinary forum for the discussion of novel post-CMOS and advanced nanoscale CMOS directions. The symposium seeks papers on innovative ideas for solutions to the principal challenge faced by integrated electronics in the 21st century: How to design, fabricate, and integrate nanosystems to overcome the fundamental CMOS limitations? In particular, such systems could:

  •  Contain unconventional nanodevices with unique capabilities, e.g., beyond simple switch behavior
  •  Introduce new logic and memory concepts
  •  Involve novel circuit styles
  •  Introduce new computing concepts
  •  Explore security architectures with nanotechnology
  •  Reconfigure and/or mask faults at much higher rates than in CMOS
  •  Require design tools and methodologies fundamental rethinking

The symposium will feature regular and special sessions, invited speakers, a best paper award, and provide extended opportunities for interaction among the participants.


Call for Papers

This 17th symposium aims to incorporate several exciting sessions on emerging computing paradigms (e.g., approximate, quantum, neuromorphic, molecular, spintronic), novel nano-based computing architectures, 2D materials (e.g., graphene) nanoelectronics and computing, beyond charge-based computing, emerging memory devices and in memory computing, nanoelectronics for biomedical systems, and to provide extended opportunities for interaction among the participants. In addition to 6-page length Regular Papers, we also invite 2-page Concept Papers presenting less developed but radical and highly innovative work in the area of nanofabrication, nanocomputing, and emerging nanosystem application.

NANOARCH 2022 topics of interest (both theoretical and experimental) include (but are not limited to):

  •  Novel nanodevices and manufacturing/integration ideas with a focus on nanoarchitectures
  •  Nanoelectronic circuits, nanofabrics, computing paradigms and nanoarchitectures
  •  Future and emergent nano-computing paradigms, e.g., approximate, quantum, neuromorphic, molecular, spintronic
  •  Paradigms and nanoarchitectures for computing with unpredictable devices
  •  Emerging memory nano-devices and in-memory computing nano-architectures
  •  Security architectures with nanofabrics
  •  Reliability-aware computing
  •  2D/3D, hybrid, defect/fault tolerant architecture, integration, and manufacturing
  •  Nanodevice and nanocircuit models, methodologies and computer aided design tools
  •  Fundamental limits of computing at the nanoscale

Important Dates

Special session proposals due: Jul 31, 2022

Special session notification of acceptance: Aug 7, 2022

Regular / special session paper submission: Aug 31, 2022
Sep 21, 2022

Notification of acceptance: Nov 3, 2022
Nov 13, 2022

Final version due: Nov 16, 2022
Nov 20, 2022

Special Session Call

NANOARCH 2022 invites proposals for special sessions that highlight new and emerging research topics.
- Special sessions will typically run for ~1.5-2 hours.
- Special session paper length: up to 6 pages.
- Invited special session papers will undergo the same review process as the regular and concept papers.

Special session topics of interest (both theoretical and experimental) include, but are not limited to:
- Nano-inspired emerging computing paradigms.
- Novel nano-based computing architectures.
- Emerging nano-devices or architectures for security.
- Nano-inspired machine learning or data analytics systems.
- Other nano-related hot topics for architectures or applications.

Special Session Submission Guidelines
The special session proposals should include:
- Topic title (~10 words)
- Organizers name and affiliation
- Session rationale and outline (~300 words)
- Session paper list with a minimum of 4 papers and no more than 2 per involved research group, including the author(s) affiliation(s), paper title, and abstract (~100-200 words)

Please send your special session proposal to the special sessions co-chairs:
- Priya Panda, priya.panda@yale.edu
- Mehdi B. Tahoori, mehdi.tahoori@kit.
- Jianlei Yang, jianlei@buaa.edu.cn

Proposals will be evaluated based on the timeliness of the topic and the qualifications of the organizers and contributors.

After the special session proposals are approved, manuscripts may be submitted to the special session and should conform to the formatting and electronic submission guidelines of regular NANOARCH papers. The invited papers, which are part of accepted special sessions proposals, will undergo the same review process as Regular and Concept papers. If, at the end of the review process, three (3) or less papers are accepted, the special session will be cancelled and the accepted papers will be moved to regular sessions.

Submission Guidelines

Authors are invited to submit of up to 6 pages in length for the Regular Paper Sessions and Special Sessions and 2 pages in length for the Concept Paper Sessions in PDF version, double column with a minimum font size of 10 points on the symposium submission website (EasyChair). Author may choose to make submissions anonymous, although that is not mandatory. The electronic submission will be considered evidence that upon acceptance, the author(s) will present their paper at the symposium. Accepted and presented papers will be submitted for inclusion to ACM Digital Library. All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript of novel unpublished work (not to exceed 6 pages of single-spaced text, including figures and tables).

All submitted papers must strictly conform to the ACM submission guidelines. Please be aware that ACM has introduced a new ACM Master Article Templates and Publication Workflow. Authors MUST follow the ACM conference paper submission guidelines, depending on their preferred platform:

Accepted and presented papers will be considered for the NANOARCH 2022 Best Paper Award as well as published in the ACM Digital Library.

After the conference, authors are invited to submit extended paper versions (containing at least 30% but preferably 50% new material) for potential publication in an IEEE Transactions on Nanotechnology NANOARCH 2022 Special issue. All papers will go through the regular IEEE Transactions on Nanotechnology review process.



Every person attending the conference MUST be registered. Registration is divided into three different periods, each with a distinct set of registration fees (Early: until Nov 27, Standard: until Dec. 1, Late: after Dec. 1). At least one Author Registration is required for each accepted paper to be included in the conference proceedings. Author Registration is open until Nov 27, 2022. Authors may include additional papers in their registration form using the optional item Extra Paper Registration.


Admission Items

Paper Author Full Conference Early (until Nov 27, 2022)
Non-Member US$250
ACM/IEEE Member US$200
Student Non-Member Non-applicable
Student ACM/IEEE Member Non-applicable
Full Conference Early (until Nov 27, 2022) Standard (until Dec. 1, 2022) Late (after Dec. 1, 2022)
Non-Member US$250 US$300 US$350
ACM/IEEE Member US$200 US$250 US$300
Student Non-Member US$50 US$60 US$70
Student ACM/IEEE Member US$40 US$50 US$60

Optional Items

Extra Paper Registration Early (until Nov 27, 2022)
Non-Member US$250
ACM/IEEE Member US$200
Student Non-Member Non-applicable
Student ACM/IEEE Member Non-applicable

Attendance Policies

As an ACM Activity, NANOARCH 2022 adoptes the ACM's Privacy Policy.

During registration, participants acknowledge ACM's Policy Against Harassment at ACM Activities and agree that behavior such as the following will constitute grounds for actions against them:
  • Abusive action directed at an individual, such as threats, intimidation, or bullying
  • Racism, homophobia, and other behavior that discriminates against a group or class of people
  • Sexual harassment of any kind, such as unwelcome sexual advances or words/actions of a sexual nature
If participants are involved in or witness any such incident, they shall inform the event organizers.

Technical Committee

Sorin D. Cotofana

Technische Universiteit Delft, The Netherlands

Joseph Friedman

The University of Texas at Dallas, USA

Swaroop Ghosh

The Pennsylvania Stat University, USA

Jie Han

University of Alberta, Canada

Xuan Hu

Apple Inc.

Honglan Jiang

Shanghai Jiao Tong University, China

Xueqing Li

Tsinghua University, China

Weiqiang Liu

Nanjing University of Aeronautics and Astronautics, China

Siting Liu

ShanghaiTech University, China

Fabrizio Lombardi

Northeastern University, USA

Marisa Lopez-Vallejo

Universidad Politecnica de Madrid, Spain

Kundan Nepal

University of St Thomas, USA

Tianxiao Nie

Beihang University, China

Ian O'Connor

Lyon Institute of Nanotechnology, France

Marco Ottavi

University of Rome Tor Vergata, Italy

Alexandru Paler

Johannes Kepler University Linz, Austria

Fei Qiao

Tsinghua University, China

Antonio Rubio

Universitat Politecnica de Catalunya, Spain

Alessandro Savino

Politecnico di Torino, Italy

Georgios Ch. Sirakoulis

Democritus University of Thrace, Greece

Mircea Stan

University of Virginia, USA

Adam Stieg

University of California - Los Angeles, USA

Ronald Tetzlaff

Technische Universität Dresden, Germany

Elena-Ioana Vatajelu

TIMA, France

Bi Wu

Nanjing University of Aeronautics and Astronautics, China

Wu Xiulong

Anhui University, China

Lang Zeng

Beihang University, China

Yongqiang Zhang

Hefei University of Technology, China

Yue Zhang

Beihang University, China


Keynote Speakers

Pierre-Emmanuel Gaillardon

University of Utah, Salt Lake City, UT, USA / RapidSilicon

"What About Increasing the Functionality of Devices Rather Than Scaling Them?"

Pierre-Emmanuel Gaillardon Exploiting unconventional physical properties, several nanodevices showed an alternative to Moore’s Law by the increase of their functionality rather than the pure scaling. Innovative device behaviors transduce to new circuit/architecture opportunities.
Here, we will introduce Three-Independent-Gate Field Effect Transistors (TIGFETs), a novel class of computation devices, that can, depending on the bias applied to its gate, achieve different modes of operations usually not achievable in a single device. The demonstrated modes of operations are (i) the dynamic reconfiguration of the device polarity; (ii) the dynamic control of the threshold voltage; and (iii) the dynamic control of the subthreshold slope beyond the thermal limit (with a measured steep slope of 6mV/dec over 5 decades of current). I will show both a silicon-based process route and a 2D approach based on WSe2 crystals. Such properties are highly desirable for logic computation. For instance, controllable-polarity devices are logical bi-conditional on both gate values and enable a compact realization of XOR-based logic functions, which are not implementable in CMOS in a compact form. Hyper regular architectures and new EDA tools are then needed to leverage the intrinsic properties of controllable-polarity devices from an application perspective.
In this talk, I will cover the different aspects of the design with TIG devices ranging from device fabrication to logic synthesis tools, emphasizing on the importance for interdisciplinary teams in the field of emerging technologies.

Short Bio: Pierre-Emmanuel Gaillardon is an Associate Professor and an adjunct Associate Professor in the School of Computing at The University of Utah, Salt Lake City, UT, where he leads the Laboratory for NanoIntegrated Systems (LNIS). He holds an Electrical Engineer M.Sc. degree from CPE-Lyon, France (2008), a M.Sc. degree in Electrical Engineering from INSA Lyon, France (2008) and a Ph.D. degree in Electrical Engineering from CEA-LETI, Grenoble, France and the University of Lyon, France (2011).
Prior to joining the University of Utah, he was a research associate at the Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland within the Laboratory of Integrated Systems (Prof. De Micheli) and a visiting research associate at Stanford University, Palo Alto, CA, USA. Previously, he was research assistant at CEA-LETI, Grenoble, France. Prof. Gaillardon is recipient of the C-Innov 2011 best thesis award, the Nanoarch 2012 best paper award, the BSF 2017 Prof. Pazy Memorial Research Award, the 2017 NSF CAREER award, the 2018 IEEE CEDA Pederson Award, the 2018 ChemE Education William H. Corcoran best paper award, the 2019 DARPA Young Faculty Award, the 2019 IEEE CEDA Ernest S. Kuh Early Career Award and the 2020 ACM SIGDA Outstanding New Faculty Award, and the 2022 ECE Department Research Award. He is a senior member of the IEEE. Prof. Gaillardon is also co-founder and CTO of RapidSilicon, an AI-enable FPGA provider and promoter of open-source technologies.
The research activities and interests of Prof. Gaillardon are currently focused on the development of novel computing systems exploiting emerging device technologies and novel EDA techniques.

Malgorzata Chrzanowska-Jeske

Portland State University, Portland, OR, USA

"3D Heterogeneous Integration Today and the Promise of Tomorrow"

Malgorzata Chrzanowska-Jeske Data-hungry applications demand increasing capacity and computational performance under low-power constraints. We face physical limits in further scaling down current silicon transistors. Contemporary architectures do not support faster communication between system components. There is hope in Heterogeneous Integration (HI): innovative three dimensional arrangements of individual chips based on starkly different technologies, silicon and non-silicon devices made of emerging materials, all integrated together into high-level systems.
Assimilating diverse technologies, architectures, and materials has enormous potential — but we face enormous implementation and design challenges. New, more efficient EDA tools based on new paradigms must take full advantage of these technologies. We will explore 3D heterogeneous ICs, their benefits and challenges, and their future potential.

Short Bio: Malgorzata Chrzanowska-Jeske is a Professor at the Electrical and Computer Engineering Department at Portland State University, and was department chair 2004-2010. She earned her M.S. from the Technical University of Warsaw, Poland, and her PhD in Electrical Engineering from Auburn University.
Her research interests include CAD for VLSI ICs, MS-SOCs, 3D ICs, nanotechnology and nano/bio systems, design for manufacturability and design issues in emerging technologies. She has given numerous plenary, keynote, and tutorial lectures at various IEEE conferences worldwide. She serves on the editorial boards of IEEE Transactions on Nanotechnology, Now Publishers’ Foundations and Trends in Integrated Circuits and Systems, and IOP Nano Express. Over the years she has served on the editorial boards of IEEE CASS II and Journal on Emerging and Selected Topics in Circuits and Systems, and as a Guest Editor for IEEE TNANO, Nanotechnology Magazine, IEEE TCAS II and other journals. She is IEEE Nanotechnology Council VP for Finances and serves on IEEE TAB Award and Recognition Committee. Previously, she served as IEEE NTC VP for Technical Activities, member of IEEE CASS BoG, and on numerous organizational, technical, and steering committees of major international conferences. She received the IEEE CEDA 2008 Donald O. Pederson Best Paper Award for the paper published in IEEEE Transactions on CAD, and the 1990 Best IEEE Transactions Paper Award from the Alabama Section. In 1993, she was awarded “Women of Distinction in Engineering Award” by Columbia Girl Scout Council. While working at the Institute of Electron Technology in Warsaw, Poland, she was a recipient of First Level Award of the Polish Ministry (Department) of Science, Higher Education and Technology for developing and Implementing NMOS-LOCOS technology for VLSI ICs (highest industrial award in Poland at that time).

J. Joshua Yang

University of Southern California, Los Angeles, CA, USA

"Memristive Devices for Neuromorphic Computing"

J. Joshua Yang In the era of ‘big data’ and ‘Internet of Things’, the traditional computing architecture based on CMOS hardware has become increasingly inefficient to support Artificial Intelligence (AI) and Machine Learning (ML), which necessitates some emerging technologies, such as memristive technology. Memristive technology was initially developed for the next-generation nonvolatile memories, for which there are still some remaining challenges to be overcome before a large-scale commercialization is feasible. On the other hand, computing applications are less constrained by such challenges and represent low-hanging fruits for memristor applications. I will first introduce the development status of memristive devices, as well as the challenges and possible solutions for those devices used for computing applications. I will then discuss a few experimental implementations of such applications with different levels of bio-inspiration.

Short Bio: J. Joshua Yang is a professor of the Department of Electrical and Computer Engineering at the University of Southern California. He was a professor of the ECE department at the University of Massachusetts Amherst between 2015 and 2020. He spent about 8 years at HP Labs between 2007 and 2015, leading the emerging devices team for memory and computing. His current research interest is Post-CMOS hardware for neuromorphic computing, machine learning and artificial intelligence, where he published several pioneering papers and holds 120 granted and about 60 pending US Patents. He is the Founding Chair of the IEEE Neuromorphic Computing Technical Committee, a recipient of the Powell Faculty Research Award and a recipient of UMass distinguished faculty lecturer and UMass Chancellor's Medal. He serves on the Advisory Boards of a number of prime international journals and conferences, including serving as an associate editor of Science Advances. Dr. Yang is a Clarivate™ Highly Cited Researcher in the field of Cross-Field and an IEEE fellow for his contributions to resistive switching materials and devices for nonvolatile memory and neuromorphic computing.

Conference Program

Note: The conference time-zone is Eastern Time (ET). Please see below the time-zone conversion of NANOARCH events:

Time-zone conversion